ADRF6720 datasheet(7/44 Pages) AD

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Data Sheet

ADRF6720

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL LOGIC

SCLK, SDIO, CS, and ENBL

Input Voltage High (VIH)

1.4

Input Voltage Low (VIL)

0.7

Input Current (IIH/IIL)

−1

µA

Input Capacitance

(CIN)

Output Voltage High

(VOH)

IOH = −100 uA

2.3

Output Voltage Low

(VOL)

IOL = 100 uA

0.2

POWER SUPPLIES

Voltage Range

VPOSx

3.3

Supply Current

Tx mode at internal LO mode (PLL, internal VCO , and modulator

enabled, LO output driver disabled)

425

Tx mode at external 1× LO mode (PLL, internal VCO disabled,

modulator enabled, LO output driver disabled)

228

LO output driver; LO_DRV_LVL bits (Register 0x22[7:6]) = 10

Power-down mode

14.5

The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) − 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF =

153.6 MHz, fREF power = 4 dBm with a 38.4 MHz fPFD. The FOM was computed at a 50 kHz offset.

Refer to Figure 47 for a plot of input impedance over frequency.

TIMING CHARACTERISTICS

Table 2.

Parameter

Description

Min

Typ

Max

Units

tSCLK

Serial clock period

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

Setup time between falling edge of CS and SCLK

Hold time between rising edge of CS and SCLK

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tACCESS

Maximum time delay between falling edge of SCLK and output data valid for a read operation

231

Maximum time delay between CS deactivation and SDIO bus return to high impedance

Figure 2. Serial Port Timing Diagram

tDS

tDH

tHIGH

tLOW

tSCLK

DON'T CARE

D15

D14

D13

DON'T CARE

SCLK

SDIO

R/W

tACCESS

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