A6986ITR datasheet(42/62 Pages) STMICROELECTRONICS

42 / 62 page

The parasitic capacitance of a real transformer mainly consists of the following contributions:

•

Capacitance across each winding (CP and CS, in the image below) due to the capacitve coupling between

the coil and the core. As already mentioned, the winding capacitances are involved in the ringing observed

during transition from the off- to on-phase of the primary side

•

Interwinding capacitance (CWW), which is the capacitance between windings. The interwinding capacitance

should be reduced in order to limit disturbance on the primary side due to possible steep voltage transitions

present in the load connected to the secondary output.

Figure 48. Transformer parasitic capacitances

CWW

7.5.3

Schottky diode

The selection of the Schottky diode should consider the following parameters:

•

Maximum forward current, mainly defined by the secondary output current demand (see equation (43));

•

Forward voltage drop, which affects the secondary output voltage regulation

•

Maximum peak reverse voltage. During the on-phase of the primary side, when in the secondary side no

current flows, the diode is reverse biased and must withstand this voltage:

VD1_rev = N∙VINmax−VOUT_pri+VOUT_sec

(44)

•

Junction capacitance, which should be as low as possible in order to reduce the ringing described in the

previous section

7.5.4

Output capacitors selection

Primary output capacitor

As in a standard buck converter, the primary output capacitor is involved in:

•

Determining the output voltage ripple

•

Supporting load transient

•

The loop stability, by setting one pole and one zero in the transfer function

Considering the ouput voltage ripple requirement, the primary output capacitance should be selected according to

the following equation:

COUT_pri=

ΔIpri

8∙fSW∙ΔVOUT_pri−ESR∙ΔIpri

(45)

Normally, MLCC capacitors are the best choice for the output capacitor, therefore the ESR contribution is

negligible and equation (46) can be simplified.

Secondary output capacitor

The secondary output capacitor supplies the secondary output load current during the tON (when diode D1 is

reverse biased) and its value defines the secondary output voltage ripple (ΔVOUT).

COUT_sec= IOUT_sec∙D

ΔVOUT_sec∙fSW

(46)

A6986I

Design of the external components

DS13481 - Rev 2

page 42/62

A6986ITR bảng dữ liệu(PDF) 42 Page - STMicroelectronics

A6986ITR bảng dữ liệu(HTML) 42 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

bảng dữ liệu tải về

Link URL