LM5145 datasheet(49/62 Pages) TI

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11.2 Layout Example

Figure 11-2 shows an example PCB layout based on the LM5146-Q1-EVM12V design. The power component

connections are made on the top layer with wide, copper-filled polygon areas. The SW connection from the

power MOSFETs to the inductor is purposely kept at minimum area to reduce radiated EMI. A power ground

plane is placed on layer 2 with 6 mil (0.15 mm) spacing to the top layer, see Figure 11-3. As a result, the buck

regulator hot loop has a small effective area based on this tightly-coupled GND plane directly underneath the

MOSFETs.

The LM5145-Q1 controller is located close to the gate terminals of the MOSFETs such that the gate drive traces

are routed short and direct. Refer to the LM5146-Q1-EVM12V Evaluation Module User's Guide for more detail.

Inductor

High-side

MOSFET

VIN

Top Layer Copper

Legend

Output Capacitor

Low-side

MOSFET

VOUT

PGND

Input

Capacitors

Layer 2 GND Plane

Top Solder

Output

Capacitor

PGND

VCC

ILIM

Copper island

connected to

AGND pin

Locate controller close

to the power stage

Use paralleled 0603 input capacitors close to

the FETs for VIN to PGND decoupling

Place PGND vias close to the

source of the low-side FET

Keep SW copper

area small

Figure 11-2. LM5145-Q1 Controller PCB Layout (Viewed From Top)

Cin1-4

VIN

GND

0.3mm

vias

Tightly-coupled return path

minimizes power loop impedance

0.15mm

Note

See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage

Layout application report for more detail.

Figure 11-3. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing

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LM5145-Q1

SNVSBU9 – JUNE 2021

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