AD9375BBCZ datasheet(9/61 Pages) AD

9 / 61 page

Data Sheet

AD9375

Rev. 0 | Page 9 of 61

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE CLOCK (DEV_CLK_IN

SIGNAL)

Frequency Range

320

MHz

Signal Level

0.3

2.0

V p-p

AC-coupled, common-mode

voltage (V

CM) = 618 mV; for

best spurious performance,

use a <1 V p-p input clock

AUXILIARY CONVERTERS

ADC

ADC Resolution

Bits

Input Voltage

Minimum

0.25

Maximum

3.05

DAC

DAC Resolution

Bits

Includes four offset levels

Output Voltage

Minimum

0.5

Reference voltage (V

REF) = 1 V

Maximum

3.0

REF = 2.5 V

Drive Capability

DIGITAL SPECIFICATIONS (CMOS),

GPIO_x, RX1_ENABLE,

RX2_ENABLE, TX1_ENABLE,

TX2 ENABLE, SYNCINBx+,

SYNCOUTB0+, GP_INTERRUPT,

SDIO, SDO, SCLK, CSB, RESET

Logic Inputs

Input Voltage

High Level

VDD_IF ×

0.8

VDD_IF

Low Level

VDD_IF ×

0.2

Input Current

High Level

−10

+10

µA

Low Level

−10

+10

µA

Logic Outputs

Output Voltage

High Level

VDD_IF ×

0.8

Low Level

VDD_IF ×

0.2

Drive Capability

DIGITAL SPECIFICATIONS (LVDS),

SYSREF_INx±, SYNCOUTB0±,

SYNCINBx± PAIRS

Logic Inputs

Input Voltage Range

825

1675

Each differentialinputin the pair

Input Differential Voltage

Threshold

−100

+100

Receiver Differential Input

Impedance

100

Internal termination enabled

Logic Outputs

Output Voltage

High

1375

Low

1025

Differential

225

Offset

1200

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