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UCD3138064RMHT bảng dữ liệu(PDF) 20 Page - Texas Instruments

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tên linh kiện UCD3138064RMHT
Giải thích chi tiết về linh kiện  UCD3138064 Highly Integrated Digital Controller for Isolated Power With 64-kB Program Flash Memory
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UCD3138064RMHT bảng dữ liệu(HTML) 20 Page - Texas Instruments

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8.9 Typical Clock Gating Power Savings
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DPWM
ADC12
Front-end Control
Peak Current
Mode
Timer
Filter
Constant
Power/Constant
Current
SCI
GIO
Module
C001
Figure 8-4. Clock Gating Power Savings
The power disable control register provides control bits that can enable or disable the clock to several
peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled
in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current
consumption of the device. The power savings chart displays the power savings per module. For example there
are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
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