IC41C82002S

IC41LV82002S

2

Integrated Circuit Solution Inc.

DR022-0A 08/20/2001

FEATURES

• Extended Data-Out (EDO) Page Mode

access cycle

• TTL compatible inputs and outputs

• Refresh Interval:

-- 2,048 cycles/32 ms

• Refresh Mode: RAS-Only,

CAS-before-RAS (CBR), and Hidden

• Self Refresh Mode 2,048 cycles/64ms

• JEDEC standard pinout

• Single power supply:

5V±10% or 3.3V ± 10%

• Byte Write and Byte Read operation via

CAS

DESCRIPTION

The

mance CMOS Dynamic Random Access Memory. The EDO

Page Mode allows 2,048 random accesses within a single row

with access cycle time as short as 20 ns per 8-bit word.

These features make the 82002S Series ideally suited for high-

bandwidth graphics, digital signal processing, high-performance

computing systems, and peripheral applications.

The 82002S Series is packaged in a 28-pin 300mil SOJ and a

28 pin 400mil TSOP-2

2M x 8 (16-MBIT) DYNAMIC RAM

WITH EDO PAGE MODE

KEY TIMING PARAMETERS

Parameter

-

50

-

60

Unit

60

ns

15

ns

30

ns

25

ns

84

104

ns

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

PRODUCT SERIES OVERVIEW

Part No.

Refresh

Voltage

IC41C82002S

2K

5V ± 10%

IC41LV82002S

2K

3.3V ± 10%

PIN DESCRIPTIONS

A0-A10

Address Inputs

I/O0-7

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

Vcc

Power

GND

Ground

NC

No Connection

PIN CONFIGURATION

28 Pin SOJ, TSOP-2