HV53001 datasheet(21/40 Pages) MICROCHIP

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DS20006518A-page 21

HV53001

3.0

DEVICE DESCRIPTION

3.1

Serial Peripheral Interface

The SPI interface is used to transfer data of the chan-

nel settings from the host controller to the high-voltage

driver. The HV53001 operates as an SPI slave device

and receives 128 bits of data from the master device

(host controller). The HV53001 SPI interface is

designed to be compatible with all Microchip 8-bit, 16-

bit and 32-bit SPI data transmission formats. This SPI

interface has a 128-bit shift register buffer to store 128

bits of data.

The SS pin is a chip select function which is similar to

the enable function to guard the clock and data input

signal. The SCK contains the bus clock signal from the

host processor. The SDI and SDO are the data input

and data output pins of the SPI shift register buffer.

SDI and SDO can be used to cascade multiple

HV53001 or HV53011 drivers together if only a single

SPI port is available. This SPI interface is compatible

with 3.3V logic input voltage with its maximum clock

frequency of 32 MHz.

The SPI shift register captures the data at the SDI

input in the rising edge of the SCK clock and pushes

out the data from the buffer to the SDO output in the

falling edge of the SCK clock. When the SPI bus is at

idle status, the SS pin stays in logic “1” and the SCK

clock is expected to stay at “0”.

FIGURE 3-1:

SPI Signal Diagram.

The bit order of the SDI data input is defined in the

following. The first and second data bits represent bit 1

and bit 0 of channel 15 in register D, respectively. The

third and fourth bits represent bit 1 and bit 0 of channel

14 in register D. This pattern is extended all the way to

channel 0. Hence, there are 32 data bits to control

The next 32 data bits are arranged in the same fashion

for register C. Similarly, the exact pattern repeats itself

for register B and A. Since each register (A, B, C and

D) contains 32 bits of data, the SPI shift register buffer

is 128 bits long.

Bit 1 of channel 15 in register D is defined as the MSb

(Most Significant bit) and bit 0 of channel 0 in register

A as the LSb (Least Significant bit) in this SPI shift

FIGURE 3-2:

SPI Bit Pattern Diagram.

* * * * * * * * * * * * * * * * * *

SCK

SDI

128 clock cycle

MSb… Data < D_CH15[1], D_CH15[0], D_CH14[1], ……. A_CH0[1], A_CH0[0] > … LSb

For example, D_CH15[1] = Setting of Register D, Channel 15, Bit 1

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