17/23

M34E02

Table 11. DC Characteristics

Note: 1. Preliminary Data.

Table 12. AC Characteristics

Note: 1. For a reSTART condition, or following a Write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Symbol

Parameter

Test Condition

(in addition to those in Table 8)

Unit

Input Leakage Current

(SCL, SDA)

± 2

µA

Output Leakage Current

± 2

µA

Supply Current

30ns)

1mA

Stand-by Supply Current

1µA

0.5

µA

Input Low Voltage

(SCL, SDA, WC)

–0.45

V

Input High Voltage

(SCL, SDA, WC)

V

E0 High Voltage

≥ 4.8V

710

V

Output Low Voltage

0.4

V

0.2

V

Test conditions specified in Table 9 and 8

Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock Frequency

100

kHz

Clock Pulse Width High

4000

ns

Clock Pulse Width Low

4700

ns

SDA Fall Time

20

300

ns

Data In Set Up Time

250

ns

Data In Hold Time

0

ns

Data Out Hold Time

200

ns

Clock Low to Next Data Valid (Access Time)

200

3500

ns

Start Condition Set Up Time

4700

ns

Start Condition Hold Time

4000

ns

Stop Condition Set Up Time

4000

ns

Time between Stop Condition and Next Start Condition

4700

ns

Write Time

10

ms