74VHC943WM datasheet(7/12 Pages) NSC

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Applications Information

TRANSMIT LEVEL ADJUSTMENT

The transmitted power levels of Table II refer to the power

delivered to a 600X load from the external 600X source

impedance The voltage on the load is half the TXA voltage

This should be kept in mind when designing interface cir-

cuits which do not match the load and source inpedances

The transmit level is programmable by placing a resistor

from TLA to VCC With a 55k resistor the line driver trans-

mits a maximum of b9 dBm Since most lines from a phone

installation to the exchange provide 3 dB of attenuation the

maximum level reaching the exchange will be b12 dBm

This is the maximum level permitted by most telephone

companies Thus with this programming the 74VHC943 will

interface to most telephones This arrangement is called the

‘‘permissive arrangement’’ The disadvantage with the per-

missive arrangement is that when the loss from a phone to

the exchange exceeds 3 dB no compensation is made and

SNR may be unnecessarily degraded

TABLE II Universal Service Order Code Resistor Values

Line

Transmit

Programming

Loss

Level

Resistor (RTLA)

(dB)

(dBm)

(X)

Open

19800

9200

5490

CARRIER DETECT THRESHOLD ADJUSTMENT

The carrier detect threshold is directly proportional to the

voltage on CDA This pin is connected internally to a high

impedance source This source has a nominal Thevenin

equivalent voltage of 12V and output impedance of 100 kX

By forcing the voltage on CDA the carrier detect threshold

may be adjusted To find the voltage required for a given

threshold the following equation may be used

VCDAe244 c VON

VCDAe345 c VOFF

CARRIER DETECT TIMING ADJUSTMENT

CDT A capacitor on Pin 4 sets the time interval that the

carrier must be present before CD goes low It also

sets the time interval that carrier must be removed

before CD returns high The relevant timing equations

are

TCDL j 64cCCDT for CD going low

TCDH j 054cCCDT for CD going high

Where TCDL

TCDH are in seconds and CCDT is in mF

DESIGN PRECAUTIONS

Power supplies to digital systems may contain high ampli-

tude spikes and other noise To optimize performance of the

74VHC943 operating in close proximity to digital systems

supply and ground noise should be minimized This involves

attention to power supply design and circuit board layout

Power supply decoupling close to the device is recommend-

ed Ground loops should be avoided For further discussion

of these subjects see the AudioRadio Handbook published

by National Semiconductor Corporation

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