PRT2011CVL5A datasheet(79/113 Pages) NXP

tên linh kiện	PRT2011CVL5A

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Electrical Characteristics

i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020

NXP Semiconductors

Figure 51 shows RMII mode timings. Table 68 describes the timing parameters (M16–M21) shown in the

figure.

Figure 51. RMII mode signal timing diagram

4.9.5

Flexible Controller Area Network (FLEXCAN) AC electrical

specifications

Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

4.9.6

LPUART electrical specifications

Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

Table 68. RMII signal timing

Characteristic

Min.

Max.

Unit

M16

ENET_CLK pulse width high

35%

65%

ENET_CLK period

M17

ENET_CLK pulse width low

35%

65%

ENET_CLK period

M18

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

—

M19

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

—

M20

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER

to ENET_CLK setup

2—

M21

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER

hold

2—

ENET_CLK (input)

ENET_TX_EN

M16

M17

M18

M19

M20

M21

ENET_RX_DATA[1:0]

ENET_TX_DATA (output)

ENET_RX_ER

ENET_RX_EN (input)

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