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LP8733 bảng dữ liệu(PDF) 17 Page - Texas Instruments |
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LP8733 bảng dữ liệu(HTML) 17 Page - Texas Instruments |
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17 / 86 page ![]() UVLO SW Reset Digital Logic Registers I2C Enable and Disable, Delay Control Slew-Rate Control Interrupts nINT SDA SCL EN VANA OTP EPROM Thermal Monitor Oscillator Buck0 ILIM Det Pwrgood Det Overload and SC Det Buck1 LDO0 LDO1 ILIM Det Pwrgood Det Overload and SC Det ILIM Det Pwrgood Det Overload and SC Det ILIM Det Pwrgood Det Overload and SC Det Ref & Bias Iload ADC Iload ADC CLKIN (GPO2) PGOOD GPO Copyright © 2016, Texas Instruments Incorporated 17 LP8733 www.ti.com SNVSBK2 – SEPTEMBER 2019 Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 DC/DC Converters 7.3.1.1 Overview The LP8733xx includes two step-down DC/DC converter cores. The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application. The cores can be configured either for a dual-phase single output configuration or for a single-phase dual output configuration. The buck regulators deliver 0.7-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply voltage. The LP8733xx has the following features: • DVS support with programmable slew rate • Automatic mode control based on the loading (PFM or PWM mode) • Forced PWM mode option • Optional external clock input to minimize crosstalk • Optional spread-spectrum technique to reduce EMI • Phase control for optimized EMI • Synchronous rectification • Current mode loop with PI compensator • Soft start |
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