HD49330AF/AHF

Rev.1.0, Apr.05.2004, page 10 of 19

Timing Chart

Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.

~

D0 to D11

D0 to D11

Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.

0

1

2

111213

N+1

N+2

N+11

N+12

N+13

N

N

−11

N

−10

N

−1N

CDSIN

SPBLK

SPSIG

ADCLK

N+2

N+10

N+11

N+12

N+13

N

−10

N

−11

N

−1

ADCIN

ADCLK

N

N+1

N

N+1

N

−12

• When CDSIN input mode is used

• When ADCIN input mode is used

Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used

• The ADC output (D0 to D11) is output at the rising edge of the ADCLK in both modes.

• Pipe-line delay is twelve clock cycles when CDSIN is used and eleven when ADCIN is used.

• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.