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CX11656 bảng dữ liệu(PDF) 21 Page - Synaptics Incorporated.

tên linh kiện CX11656
Giải thích chi tiết về linh kiện  Home Networking Physical Layer Device with Integrated Analog Front End Circuitry Data Sheet (Preliminary)
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CX11656 HomePlug 1.0 PHY Data Sheet
102069A
Conexant Proprietary and Confidential Information
3-1
3.
CX11656 Functional Description
The interfaces that provide data, status, and control to and from the CX11656 include:
•
External host interface provided via the Media Independent Interface (MII) format
(described by IEEE 802.3u, Clause 22) or a General Purpose Serial Interface (GPSI)
•
Management control provided via the Management Data Interface (MDI) or the
Serial Peripheral Interface (SPI)
•
Analog Front End interface
•
LEDs indicating network status
•
Optional EEPROM interface providing a path to initialize the CX11656
•
The JTAG port implements the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
A block diagram of the CX11656 PHY is shown in Figure 3-1.
Figure 3-1. CX11656 PHY Block Diagram
102069_005
MII/GPSI
Interface
RISC
uProcessor Core
Interface
DMA
Buffer
RAM
Link
Sequencer
Arbiter
Configuration
Registers
ADIO[9:0]
MDI
or SPI
JTAG
PHY
Seq
PHY
Core
AFE
Logic
FIFOs
SPI
Master
PHY
DMA
ROM
ROM
LEDs
Interface Block
MAC
PHY
AGC [7:0]
MDII
or GPSI
TEST
EEPROM
CX11656



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