AD9988 datasheet(29/40 Pages) AD

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Data Sheet

AD9988

TYPICAL PERFORMANCE CHARACTERISTICS

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Rev. 0 | 29 of 40

Figure 24. DAC0 Fundamental Output Power vs. fOUT Across fDAC, at 0

dBFS Digital Back Off, Measured on a Laboratory Evaluation Board; the

AD9081-FMCA-EBZ or AD9082-FMCA-EBZ Evaluation Board has a Different

PCB Layout and Results in a Different Frequency Response when Compared

to a Laboratory Evaluation Board

Figure 25. Single Sideband Phase Noise vs. Frequency Offset for Different

Clock Input Power (PCLK ), fOUT= 1.8 GHz, External 12 GHz Clock Input with

Clock PLL Disabled

Figure 26. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over

fDAC, Shuffle On, 16-Bit Resolution, Mode 15C

Figure 27. Single Sideband Phase Noise vs. Frequency Offset for Different

PLL Reference Clocks (fREF), fOUT = 1.8 GHz, fDAC = 12 GSPS, PLL Enabled

with Exception of External 12 GHz Clock Input with Clock PLL Disabled

Figure 28. Single Sideband Phase Noise vs. Frequency Offset for Different

DAC Output Frequencies (fOUT), External 12 GHz Clock Input with Clock PLL

Disabled

Figure 29. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over

fDAC, 12-Bit Resolution, Shuffle On, Mode 24C

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