PCI1520 datasheet(42/140 Pages) TI

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3−7

Table 3−3. Functionality of the ZV Output Signals

INPUTS

OUTPUTS

PORTSEL

SOCKET 0 ENABLE

SOCKET 1 ENABLE

ZVSEL0

ZVSEL1

ZVSTAT

Also shown in Figure 3−5 is a third ZV input that can be provided from a source such as a high-speed serial bus like

IEEE 1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an active-high output

indicating that one of the PCI1520 sockets is enabled for ZV mode. The implementation shown in Figure 3−5 can be

used if PC Card ZV is prioritized over other sources.

3.5.4

Standardized Zoomed-Video Register Model

The standardized zoomed-video register model is defined for the purpose of standardizing the ZV port control for PC

Card controllers across the industry. The following list summarizes the standardized zoomed-video register model

changes to the existing PC Card register set.

•

Socket present state register (CardBus socket address + 08h, see Section 6.3)

Bit 27 (ZVSUPPORT) has been added. The platform BIOS can set this bit via the socket force event register

(CardBus socket address + 0Ch, see Section 6.4) to define whether zoomed video is supported on that

socket by the platform.

•

Socket force event register (CardBus socket address + 0Ch, see Section 6.4)

Bit 27 (FZVSUPPORT) has been added. The platform BIOS can use this bit to set the ZVSUPPORT bit in

the socket present state register (CardBus socket address + 08h, see Section 6.3) to define whether

zoomed video is supported on that socket by the platform.

•

Socket control register (CardBus socket address +10h, see Section 6.5)

Bit 11 (ZV_ACTIVITY) has been added. This bit is set when zoomed video is enabled for either of the PC

Card sockets.

Bit 10 (STDZVREG) has been added. This bit defines whether the PC Card controller supports the

standardized zoomed-video register model.

Bit 9 (ZVEN) is provided for software to enable or disable zoomed video, per socket.

If the STDZVEN bit (bit 0) in the diagnostic register (PCI offset 93h, see Section 4.34) is 1, then the standardized

zoomed video register model is disabled. For backward compatibility, even if the STDZVEN bit is 0 (enabled), the

PCI1520 allows software to access zoomed video through the legacy address in the card control register (PCI offset

91h, see Section 4.32), or through the new register model in the socket control register (CardBus socket address +

10h, see Section 6.5).

3.5.4.1 Zoomed-Video Card Insertion and Configuration Procedure

A zoomed-video PC Card is inserted into an empty slot.

The card is detected and interrogated appropriately.

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