ICS9DB306BLLF datasheet(8/16 Pages) ICST

8 / 16 page

9DB306BL

www.icst.com/products/hiperclocks.html

REV. A APRIL 7, 2005

Integrated

Circuit

Systems, Inc.

ICS9DB306

PCI EXPRESS,

JITTER ATTENUATOR

CC - 2V

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

o = 50Ω

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion.

Figures 3A and 3B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

TERMINATION FOR LVPECL OUTPUTS

FIGURE 3B. LVPECL OUTPUT TERMINATION

FIGURE 3A. LVPECL OUTPUT TERMINATION

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