M16U4G16256A datasheet(4/53 Pages) ESMT

4 / 53 page

ESMT

M16U4G16256A

Elite Semiconductor Memory Technology Inc

Publication Date : Jan. 2020

Revision : 1.1

4/53

Input / Output Functional Description

Symbol

Type

Function

CK_t, CK_c

Input

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

CKE

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any

bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have

become stable during the power on and initialization sequence, they must be maintained

during all operations (including Self-Refresh). CKE must be maintained high throughout

read and write accesses. Input buffers, excluding CK_t

during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.

CS_n

Input

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for

external Rank selection on systems with multiple Ranks. CS_n is considered part of the

command code.

ODT

Input

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance

internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,

DQS_c and DM_n/DBI_n/ TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode

to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT

pin will be ignored if MR1 is programmed to disable RTT_NOM.

ACT_n

Input

Activation Command Input : ACT_n defines the Activation command being entered along

with CS_n. The input into RAS_n, CAS_n/A15 and WE_n/A14 will be considered as Row

Address A15 and A14

RAS_n, CAS_n/A15,

WE_n/A14

Input

Command Inputs: RAS_n, CAS_n/A15 and WE_n/A14 (along with CS_n) define the

command being entered. Those pins have multi function. For example, for activation with

ACT_n Low, those are Addressing like A15, A14 but for non-activation command with

ACT_n High, those are Command pins for Read, Write and other command defined in

command truth table

DM_n/DBI_n

(DMU_n/DBIU_n),

(DML_n/DBIL_n)

Input/Output

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.

Input data is masked when DM_n is sampled LOW coincident with that input data during a

Write access. DM_nis sampled on both edges of DQS. DM is muxed with DBI function by

Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or TDQS is

enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying

whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/

output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH.

BG0 - BG1

Input

Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or

Precharge command is being applied. BG0 also determines which mode register is to be

accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0

BA0 - BA1

Input

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. Bank address also determines which mode register is to be

accessed during a MRS cycle.

M16U4G16256A bảng dữ liệu(PDF) 4 Page - Elite Semiconductor Memory Technology Inc.

M16U4G16256A bảng dữ liệu(HTML) 4 Page - Elite Semiconductor Memory Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

bảng dữ liệu tải về

Link URL