LT1168 datasheet(13/28 Pages) AD

13 / 28 page

LT6372-1

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

–RG,F (Pin 1/Pin 19): For use with an external gain setting

resistor. This connection should be routed to the gain set-

ting resistor separately from –RG,S in order to minimize

gain errors.

–RG,S (Pin 2/Pin 20): For use with an external gain set-

ting resistor. This connection should be routed to the gain

setting resistor separately from –RG,F in order to minimize

gain errors.

–IN (Pin 4/Pin 2): Negative Input Terminal. This input is

high impedance.

+IN (Pin 5/Pin 5): Positive Input Terminal. This input is

high impedance.

CLLO (Pin 7/Pin 8): Low Side Clamp Input. The voltage

applied to the CLLO pin defines the lower voltage limit

of the output. Typically, the output clamps 500mV below

the voltage applied to the CLLO pin. Do not float CCLO.

V– (Pin 8/Pin 7): Negative Power Supply. A bypass capac-

itor should be used between supply pins and ground.

CLHI (Pin 9/Pin 10): High Side Clamp Input. The voltage

applied to the CLHI pin defines the upper voltage limit of

the output. Typically, the output clamps 500mV above the

voltage applied to the CLHI pin. Do not float CLHI.

REF1 (Pin 10/Pin 12): Reference for the output voltage.

REF1 can be tied to REF2 and used as a reference for the

output. REF1 can also be used with REF2 to form a voltage

divider and level shift the output.

OUTPUT (Pin 11/Pin 13): Output voltage referenced to

the REF pins.

V+ (Pin 12/Pin 14): Positive Power Supply. A bypass

capacitor should be used between supply pins and ground.

REF2 (Pin 13/Pin 15): Reference for the output voltage.

REF2 can be tied to REF1 and used as a reference for the

output. REF2 can also be used with REF1 to form a voltage

divider and level shift the output.

+RG,S (Pin 15/Pin 17): For use with an external gain set-

ting resistor. This connection should be routed to the gain

setting resistor separately from +RG,F in order to minimize

gain errors.

+RG,F (Pin 16/Pin 18): For use with an external gain set-

ting resistor. This connection should be routed to the gain

setting resistor separately from +RG,S in order to minimize

gain errors.

NIC (Pins 3, 6, 14/Pins 1, 3, 4, 6, 11, 16): No Internal

Connection.

DNC (QFN Pin 9): Do Not Connect. This pin should float.

(MS16E/QFN20)

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