5.2.2

I²C read and write sequences

The previous sequences are used to implement actual write and read sequences described in the tables below.

Transfer when the master is writing one byte to slave:

Master

ST

SAD+W

SUB

DATA

SP

Slave

SAK

SAK

SAK

Transfer when master is writing multiple bytes to slave:

Master

ST

SAD+W

SUB

DATA

DATA

SP

Slave

SAK

SAK

SAK

SAK

Transfer when master is receiving (reading) one byte of data from slave:

Master

ST

SAD+W

SUB

SR

SAD+R

NMAK

SP

Slave

SAK

SAK

SAK

DATA

Transfer when master is receiving (reading) multiple bytes of data from slave:

Master

ST

SAD+W

SUB

SR

SAD+R

MAK

MAK

NMAK

SP

Slave

SAK

SAK

SAK

DATA

DATA

DATA

Data are transmitted in byte format. Each data transfer contains 8 bits. The number of bytes transferred per

transfer is unlimited. Data is transferred with the Most Significant Bit (MSB) first. If a receiver can’t receive another

complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the

transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is

performing some real-time function) the data line must be left HIGH by the slave. The Master can then abort the

transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition

(SP). Each data transfer must be terminated by the generation of a STOP condition.

STTS22H

I²C interface

DS12606 - Rev 4

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