AD9546SLASHPCBZ datasheet(100/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 100 of 205

DISTRIBUTION N SHOT/PRBS OUTPUT CLOCKING

N SHOT/PRBS CLOCKING OVERVIEW

The Q dividers work in conjunction with several controllers, one

of which is the N shot/pseudorandom binary sequence (PRBS)

controller (see Figure 67). The N shot/PRBS controller provides

the AD9546 with the capability of generating SYSREF and

device clock clocks per the JESD204B standard as well as gapped

and pseudorandom clock signals.

Figure 68 shows a block diagram of the N shot/PRBS clock

controller, which includes a more detailed representation of the

relationship between the Q dividers, the modulation controller

and the N shot/PRBS controller. Although Figure 68 is specific

to PLL0, it is also representative of PLL1, because there are

dedicated controllers for each PLL channel.

Regarding the Q dividers, Qxy denotes a specific Q divider in

the clock distribution section, whereas Qxy denotes the output

of divider Qxy (where x is 0 and y is A, AA, B, BB, C, or CC).

For example, Q0A is the output of Q divider Q0A.

Note that the Q0AA, Q0BB, and Q0CC outputs route directly to the

N shot/PRBS controller, whereas Q0A, Q0B, and Q0C route

through the modulation controller. As such, the Q0A, Q0B, and

Q0C outputs are the only outputs subject to modulation (see the

Distribution Embedded Output Clock Modulation section).

However, disabled (default) modulation channels have an

internal bypass allowing the Q0A, Q0B, and Q0C outputs to pass

directly through the modulation controller.

FROM

SYSTEM

CLOCK

FROM

PLL0

Q DIVIDER PAIR

N SHOT/PRBS CONTROLLER

TRIGGER

GAP

OUT

PRBS GENERATOR A

N SHOT/PRBS GENERATOR A

Mx PIN

FUNCTION

LOGIC

PINS

OUTPUT

DRIVERS

N SHOT GENERATOR A

MODE

Q DIVIDER PAIR

Q0CC

MODULATION

CONTROLLER

FEEDBACK

DPLL0

N DIVIDER

SIGA

N SHOT RETIMING MUX

N SHOT

REQUEST

OUT0AN

HITLESS/

ZERO DELAY

FEEDBACK

AND SYNC

TRIGGER

MODE

GAP

REG 0x2101,

BIT 0

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES SHOWN ARE SPECIFIC TO Q DIVIDER PAIR Q0x (WHERE x = A, AA, B, BB, C, OR CC), PLL CHANNEL 0,

N SHOT/PRBS GENERATOR A, AND TRANSLATION PROFILE 0.0

3. SEE THE MODULATION SYNCHRONIZATION SECTION FOR DETAILS ABOUT THE SNCx AND SIGx SIGNALS

Q0C

Q0BB

Q0B

Q0AA

Q0A

REG 0x10DA,

BIT 1

REG 0x1202, BITS[4:0]

REG 0x1203, BITS[4:2]

REG 0x10D3, BITS[5:0]

REG 0x10D2, BITS[7:0]

REG 0x10D3, BIT 6

REG 0x10D6,

BIT 4

REG 0x10D6,

BIT 0

OUT0BP

OUT0BN

OUT0CP

OUT0CN

Figure 68. Block Diagram of JESD204B/Gapped Clock Controller

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