DWM3000 Datasheet

© Qorvo 2020

Preliminary

Version 0.1

Page 7

1.3.2 SPI Operating Modes

Both clock polarities (SPIPOL=0/1) and phases (SPIPHA=0/1) are supported, as defined in the Motorola SPI

protocol. The DW3110 transfer protocols for each SPIPOL and SPIPHA setting are given in Figure 5 and Figure

6.

Figure 5: DW3000 SPIPHA=0 Transfer Protocol

Figure 6: DW3000 SPIPHA=1 Transfer Protocol

SPIPOL=0, SPIPHA=0

z

MSB

6

5

4

3

2

1

LSB

SPICLK

SPICSn

Cycle

Number, #

SPIMISO

SPIMOSI

SPIPOL=1, SPIPHA=0

SPICLK

z

MSB

6

5

4

3

2

1

LSB

1

2

3

4

5

6

7

8

MSB

LSB

MSB

LSB

9

8*Number of

bytes

X

X

Z

Z

SPIPOL=0, SPIPHA=1

z

MSB

6

5

4

3

2

1

LSB

SPICLK

SPICSn

Cycle

Number, #

SPIMISO

SPIMOSI

SPIPOL=1, SPIPHA=1

SPICLK

z

MSB

6

5

4

3

2

1

LSB

1

2

3

4

5

6

7

8

MSB

LSB

MSB

LSB

9

8*Number of

bytes

X

X

Z

Z