2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS04

to the receiving device(s).

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curves

2

3

2

4

2

3

Input ± 32 kHz

2

4

± 1 kHz

Figure 9-2. Application timing diagram

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SN74HCS04

SCLS796B – JANUARY 2020 – REVISED JANUARY 2021

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