LAN7430SLASHY9X datasheet(25/77 Pages) MICROCHIP

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 2018-2019 Microchip Technology Inc.

DS00002631D-page 25

LAN7430/LAN7431

3.4

Configuration Straps

Configuration straps are latched on Power-On Reset (POR) and External Chip Reset (RESET_N) and are identified by

an underlined symbol name. Configuration straps are multi-function pins that are driven as outputs during normal oper-

ation. During a Power-On Reset (POR) or an External Chip Reset (RESET_N), these outputs are not driven. The high

or low state of the signal is latched following deassertion of the reset and is used to determine the default configuration

of a particular feature. The following configuration strap signals are available:

• ADV_PM_DISABLE

• MII_EN (LAN7431 only)

Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a partic-

ular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal

resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden

by the addition of an external resistor. When externally pulling configuration straps high, the strap should be tied to

VDDVARIO or VDDVARIO_B as indicated in the pin descriptions.

The system designer must ensure that configuration straps meet the timing requirements specified in Section 7.6.3,

"Power-On Configuration Strap Timing" and Section 7.6.4, "Reset Pin Configuration Strap Timing". If configuration

straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values.

PCIe Ground

GD_1

GD_2

GD_3

PCIe ground.

Ground

VSS

Common ground.

This exposed pad must be connected to the ground plane

with a via array.

Note:

Configuration straps must never be driven as inputs. If required, configuration straps can be augmented,

or overridden with external resistors.

TABLE 3-3:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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