AD4021 datasheet(10/39 Pages) AD

10 / 39 page

AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 10 of 39

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF 1

VDD 2

IN+ 3

IN– 4

GND 5

VIO

SDI

SCK

SDO

CNV

AD4020/

AD4021/

AD4022

TOP VIEW

(Not to Scale)

Figure 3. 10-Lead MSOP Pin Configuration

REF

VDD

IN+

IN–

GND

10 VIO

9SDI

8SCK

7SDO

6CNV

AD4020/

AD4021/

AD4022

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED

PAD TO GND. THIS CONNECTION IS NOT

REQUIRED TO MEET THE SPECIFIED

PERFORMANCE.

Figure 4. 10-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

REF

Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be

decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor.

VDD

1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor.

IN+

Differential Positive Analog Input. See the Differential Input Considerations section.

IN−

Differential Negative Analog Input. See the Differential Input Considerations section.

GND

Power Supply Ground. Connect to the ground plane of the board.

CNV

Convert Input. This input has multiple functions. On the leading edge, the input initiates the conversions

and selects the interface mode of the device, which is either daisy-chain mode or CS mode. In CS mode,

the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high.

SDO

Serial Data Output. The conversion result is output on this pin. The pin is synchronized to the SCK signal

on the SCK pin.

SCK

Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.

SDI

Serial Data Input. This input provides multiple features and selects the interface mode of the ADC as

follows.

Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data

input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data

level on SDI is output on SDO with a delay of 20 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable

the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator

feature is enabled. With CNV low, program the device by clocking in a 16-bit word on SDI on the rising

edge of SCK.

VIO

Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V). Bypass VIO to ground with a 0.1 μF ceramic capacitor.

N/A2

EPAD

Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet the specified

performance. Note that the exposed pad only applies to the LFCSP.

1 AI is analog input, P is power, DI is digital input, and DO is digital output.

2 N/A means not applicable.

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