© 2018 Integrated Device Technology, Inc.

13

Rev O May 11, 2018

F1421 Datasheet

Power-On Procedure

Set up the voltage supplies and Evaluation Board as described in the "Power Supply Setup" section with the "Standby Pin” set for logic LOW.



Enable the power supply.



The STBY pin now can now be exercised.

Power-Off Procedure



Set the STBY pin to logic LOW.



Disable the power supply.

Application Information

The F1421 has been optimized for use in high-performance RF applications from 1.7GHz to 2.2GHz.

Standby Mode (STBY)

The F1421 has a standby pin which allows the amplifier to be turned off to decrease overall power requirements. The pin uses simple logic

levels and is compatible with both JEDEC 1.8V and JEDEC 3.3V logic. Table 7 lists the amplifier state for the logic. An internal pull-down resistor

causes the amplifier to default to the on state.

Table 7.

Standby Truth Table

STBY (pin 8)

Condition

LOW or Open

Amplifier On

HIGH

Amplifier Off

RSET and RDSET

The F1421 has been optimized for gain and intermodulation products by adjusting the bias resistors RSET and RDSET. For the optimized

setting, RSET (R1) is 1.87kΩ and RDSET (R2) is 5.11kΩ.

Power Supplies

The power supply pin should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade the noise

figure, and fast transients can trigger ESD clamps and cause them to fail. Supply voltage changes or transients should have a slew rate less

than 1V/20µs.