© 2018 Integrated Device Technology, Inc.

13

Rev O January 23, 2018

F1420 Datasheet

Power-On Procedure

Set up the voltage supplies and Evaluation Board as described in the "Power Supply Setup" section and set the "Standby Pin” or logic LOW.

Enable the power supply.

The STBY pin now can now be exercised.

Power-Off Procedure

Set the STBY pin for logic LOW.

Disable the power supply.

Application Information

The F1420 has been optimized for use in high performance RF applications from 700MHz to 1100MHz.

Standby Mode (STBY)

The F1420 has a standby pin that allows the amplifier to be turned off to decrease overall power requirements. The pin uses simple logic levels

and is compatible with both JECEC 1.8V and JEDEC 3.3V logic. Table 7 lists the amplifier state for the logic. An internal pull-down resistor

causes the amplifier to default to the on state.

Table 7.

Standby Truth Table

STBY (pin 8)

Condition

LOW or Open

Amplifier On

HIGH

Amplifier Off

RSET and RDSET

The F1420 has been optimized for gain and intermodulation products by adjusting the bias resistors RSER and RDSET. For the optimized

setting, the values are RSET (R1) is 2.26kΩ and RDSET (R2) is 5.76kΩ.

Power Supplies

The power supply pin should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure

and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than

1V/20μs.

Control Pin Interface

If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit

at the input of each control pin is recommended. This applies to control pin 8 (STBY). Note the recommended resistor and capacitor values do

not necessarily match the EVKit BOM for the case of poor control signal integrity.