ZSSC3036 datasheet(7/49 Pages) RENESAS

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ZSSC3036 Datasheet

April 20, 2016

A dynamic power-on-reset circuit is implemented in order to achieve minimum current consumption in idle mode.

The VDD low level and the subsequent rise time and VDD rising slope must meet the requirements in Table 1.1 to

guarantee an overall IC reset; lower VDD low levels allow slower rising of the subsequent on-ramp of VDD. Other

combinations might also be possible. For example, the reset trigger can be influenced by increasing the power-

down time and lowering the VDD rising slope requirement.

Table 1.3

Requirements for VDD Power-on Reset

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Power Down Time (duration of VDD Low Level)

tSPIKE

µs

VDD Low Level

VDDlow

0.2

VDD Rising Slope

SRVDD

V/ms

1.3.

Electrical Parameters

All parameter values are valid only under the specified operating conditions. All voltages are referenced to Vss.

Table 1.4

Electrical Parameters

Note: See important table notes at the end of the table.

Parameter

Symbol

Conditions/Comments

Min

Typ

Max

Unit

Supply

Bridge Supply Voltage,

ADC Reference Voltage

VDDB

Internally generated

1.60

1.67

1.74

Current Consumption

IVDD

Active State, average

900

1500

µA

Sleep State, idle current,

≤ 85°C

250

Sleep State, idle current,

≤110°C

950

Power Supply Rejection

20·log10(VDD/VDDB)

(see section 1.4)

PSRVDD

VDD = 1.8V

VDD = 2V

Memory Program Voltage

VDD,prog

Required voltage level at VDD pin

2.9

3.6

Mean Program Current

IVDD,prog

Mean current consumption during

MTP programming cycle at VDD

Peak Program Current

Iprog,max

MTP programming at VDD pin,

dynamic switch-on current draw

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