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LTC4255 bảng dữ liệu(PDF) 8 Page - Linear Technology |
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LTC4255 bảng dữ liệu(HTML) 8 Page - Linear Technology |
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8 / 16 page ![]() LTC4255 8 4255f Figure 2. Current Limit Timing Figure 3. Open-Circuit Filter Timing Figure 4. Turn-On Delay Figure 1. 2-Wire Interface Timing TEST TI I G SCL SDA FAULT t1 t2 t3 tr tf t5 t6 t7 t8 t9 t4 4255 F01 0V VSENSE TO VEE FAULT tCL 4255 F02 VSC 0V VSENSE TO VEE FAULT tOCF 4255 F03 VOC tOD 4255 F04 AO ACK STOP BIT SCL SDA GATE REGISTER DEFI ITIO S Register 4: Status Register 2 (Read Only) D0: Current Limit Fault Status for Port 1. Logic high indicates a short-circuit has been detected on Port 1. D1: Current Limit Fault Status for Port 2. Logic high indicates a short-circuit has been detected on Port 2. D2: Current Limit Fault Status for Port 3. Logic high indicates a short-circuit has been detected on Port 3. D3: Current Limit Fault Status for Port 4. Logic high indicates a short-circuit has been detected on Port 4. D4: Open-Circuit Fault Status for Port 1. Logic high indicates an open-circuit has been detected on Port 1. D5: Open-Circuit Fault Status for Port 2. Logic high indicates an open-circuit has been detected on Port 2. D6: Open-Circuit Fault Status for Port 3. Logic high indicates an open-circuit has been detected on Port 3. D7: Open-Circuit Fault Status for Port 4. Logic high indicates an open-circuit has been detected on Port 4. |
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