DP83241BV datasheet(4/20 Pages) NSC

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20 Functional Description

The CDD device clocks are all generated from and phase

aligned to either a 125 MHz crystal oscillator or a TTL input

reference source using digital phase locked loop tech-

niques The architecture of the Clock Distribution Device en-

sures that the output clocks which are generated have fre-

quency tolerances identical to the 50 PPM crystal reference

When the reference input signal is a backplane signal the

matching of the phase comparator input path delays guar-

antees phase alignment within 3 ns

The phase locked loop generates the desired clocks as

shown in the device Block Diagram One of the Local Byte

Clock (LBC) phases is connected to the FEEDBK IN input of

the phase comparator where its phase and frequency are

compared against that of the selected input reference sig-

nal Any phase error between these signals results in a cor-

rection of the voltage into the Voltage Controlled Oscillator

(VCO) which is proportional to the amount of phase error

The correction voltage tends to drive the frequency of the

VCO in the direction which when divided down minimizes

the LBC to reference signal phase difference When the

phase transition of the LBC occurs before that of the refer-

ence input the VCO frequency is sensed as being too fast

and produces a negative going correction to the VCO input

This in turn slows down the VCO’s frequency and delays the

subsequent LBC phase transitions

The device’s differential 125 MHz ECL transmit clock and

differential 125 MHz ECL load strobe are used by the

PLAYER device to convert data from byte wide NRZ format

to serial NRZI format for fiber medium transmission A

125 MHz TTL local byte clock is provided for use by the

PLAYER and the BMAC devices Five phases of the local

byte clock are provided for use in large multi-board concen-

trator configurations to aid in cancelling out backplane de-

lays A 25 MHz Local Symbol Clock (LSC) is provided which

is in phase with the local byte clocks and has a 40% HIGH

and 60% LOW duty cycle

The device provides three user-selectable features The

REF SEL input provides the option to lock the device’s out-

puts to a crystal oscillator or to an external TTL signal (REF

IN) The REF IN signal is particularly useful in concentrators

where multiple boards need to be phase locked to a com-

mon reference signal The VCO SEL input provides the op-

tion to use the internally provided VCO or an external LC

voltage controlled oscillator Although the stability of the in-

ternal VCO should be adequate for most applications the

external VCO option provides the means of obtaining the

maximum possible oscillator Q The PHASE SEL input pin

provides the option of selecting whether the five phase LBC

outputs are phase offset 36 degrees or 72 degrees (8 ns or

16 ns)

The phase locked loop (PLL) elements with the exception

of the loop filter which consist of two capacitors and a resis-

tor are fully contained within the device The internal VCO

associated with the PLL has been implemented totally with-

in the device and requires no external LC oscillator tank

coils capacitors or varactors The external VCO option

does provide a means of using these conventional LC oscil-

lator techniques if desired

Connection Diagram

28-Pin PLCC Package

TLF10385 – 25

Order Number DP83241BV

See NS Package Number V28A

FIGURE 2-1 DP83241 Pinout

Block Diagram

TLF10385 – 3

FIGURE 2-2 DP83241 Block Diagram

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