CDC950

133MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR

PC MOTHERBOARDS/SERVERS

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

12

POST OFFICE BOX 655303

APPLICATION INFORMATION

HCLK

MultSel0

MultSel1

CDC950

HCLK

TLA

TLB

R(S1) = 33 Ω

R(S1) = 33 Ω

RI(REF) = 475 Ω

R(T1) = 49.9 Ω

R(T1) = 49.9 Ω

CL = 2 pF

CL = 2 pF

CL Represents CBOARD and Cjig

ZTLA = ZTLB = 50 Ω

VDD

HCLK

HCLK

Figure 2. Load Circuit for HCLK Bus

spread spectrum clock (SSC) implementation for CDC950

Simultaneously switching at a fixed frequency generates a significant power peak at the selected frequency,

which in turn causes EMI disturbance to the environment. The purpose of the internal frequency modulation of

the CPU-PLL allows energy to be distributed to many different frequencies which reduces the power peak.

A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in

Figure 3.

∆

Maximum Peak

SSC

δ of f(nom)

f(nom)

Non-SSC

Figure 3. Frequency Power Spectrum With and Without the Use of SSC

The modulated spectrum has its distribution (left side) associated with the single-frequency spectrum which

indicates a down-spread modulation.

The peak reduction depends on the modulation scheme and modulation profile. System performance and timing

requirements are the limiting factors for actual design implementations. The implementation was driven to keep

the average clock frequency close to its upper specification limit. The modulation amount was set to

approximately –0.6%.

To allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation signal

is limited in order to minimize SSC induced tracking skew jitter. The modulation frequency is approximately

31 kHz.