STPD01PUR datasheet(31/43 Pages) STMICROELECTRONICS

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Figure 41. Capacitor placing

The layout of decoupling capacitors is extremely important to minimize the induction loop formed between the

capacitor and the IC power and ground. The vias should be placed on the side of the capacitor lands, not the

ends. The vias should be located at minimum keepout distance and connected to the capacitor lands with a wide

trace - at least as wide as the via pad. Vias of opposite polarity should be placed as close together as possible

(minimum keepout distance) and vias of the same polarity should be kept separated as much as possible. If

space allows, a second pair of vias on the opposite side of the capacitor may be added to reduce the inductance

further.

Inductor placing

The DC-DC converter inductor has to be placed as close as possible with traces as short and as thick as

possible. This should be done to minimize resistive parasitic effects, and increase system efficiency.

Figure 42. Inductor placing

Vias placing

It is crucial to connect very well the ground of the exposed pad of the QFN24L to the ground on the application

board. Therefore many vias are necessary to be sure that the parasitic inductor introduced from each via is

negligible.

STPD01

Board layout guidelines

DS13473 - Rev 1

page 31/43

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