STPD01 datasheet(23/43 Pages) STMICROELECTRONICS

23 / 43 page

The master then generates further SCL cycles to either transmit data to the slave or receive data from the slave.

At the end of the data transfer, the master generates the stop command and the bus is released and all devices

wait for a new start command.

7.12.1

Read and write commands

The format of I2C commands is described below. All figures use common format and symbols. Every data word

consists of eight bits with most significant bit first and least significant bit last.

Write command to the transceiver device is described by the following figure. It is possible to write to several

consecutive registers during one write command.

Figure 39. Write command

Slave Address

R/W

Data

7 bits

8 bits

“0” Write

From Master to Slave

From Slave to Master

A = acknowledge (SDA LOW)

S = START condition

P = STOP condition

Read command consists of dummy write to set the proper address of a register followed by a real read

sequence.

Figure 40. Read command

Slave Address

R/W

Slave Address

7 bits

8 bits

“0” Write

From Master to Slave

From Slave to Master

A = acknowledge (SDA LOW)

S = START condition

P = STOP condition

Sr = Repeated Start

R/W

7 bits

8 bits

“1” Write

The master sends a “Repeated Start” after sending the register address and before resending the slave address.

The “Repeated Start” is defined as SDA transition from 1 to 0 with SCL high.

7.12.2

I2C address selection

The I2C address can be selected using the ADD pin to allow multiple devices to be connected on the same bus.

The address is composed as below:

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ADD1

ADD0

R/W

STPD01

Bus timing

DS13473 - Rev 1

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