STM32L552CCT3PXXX datasheet(55/340 Pages) STMICROELECTRONICS

55 / 340 page

DS12737 Rev 6

55/340

STM32L552xx

Functional overview

3.15

Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 13: DMA1 and DMA2 implementation for the

features implementation.

Direct memory access (DMA) is used in order to provide a high-speed data transfer

between peripherals and memory as well as from memory to memory. Data can be quickly

moved by DMA without any CPU actions. This keeps the CPU resources free for other

operations.

The two DMA controllers have 16 channels in total, each one dedicated to manage memory

access requests from one or more peripherals. Each controller has an arbiter for handling

the priority between DMA requests.

The DMA supports 8 channels for each DMA1 and DMA2, independently configurable:

•

Each channel is associated either with a DMA request signal coming from a peripheral,

or with a software trigger in memory-to-memory transfers. This configuration is done by

software.

•

Priority between the requests is programmable by software (4 levels per channel: very

high, high, medium, low) or by hardware in case of equality (such as request 1 has

priority over request 2).

•

Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be aligned

on the data size.

•

Support of transfers from/to peripherals to/from memory with circular buffer

management.

•

Programmable number of data to be transferred: 0 to 218 - 1.

•

Generation of an interrupt request per channel. Each interrupt request is caused from

any of the three DMA events: transfer complete, half transfer, or transfer error.

•

TrustZone support:

–

Support for AHB secure and non-secure DMA transfers, independently at a first

channel level, and independently at a source and destination sub-level

–

TrustZone-aware AHB slave port, protecting any secure resource (register,

•

Privileged / unprivileged support:

–

Support for AHB privileged and unprivileged DMA transfers, independently at a

channel level

–

Privileged-aware AHB slave port.

Table 13. DMA1 and DMA2 implementation

Feature

DMA1

DMA2

Number of DMA channels

TrustZone

1 (supported)

STM32L552CCT3PXXX bảng dữ liệu(PDF) 55 Page - STMicroelectronics

STM32L552CCT3PXXX bảng dữ liệu(HTML) 55 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL