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STM32L552CC bảng dữ liệu(PDF) 77 Page - STMicroelectronics |
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STM32L552CC bảng dữ liệu(HTML) 77 Page - STMicroelectronics |
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77 / 340 page ![]() DS12737 Rev 6 77/340 STM32L552xx Functional overview 78 The SDMMC features include the following: • Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (backward compatibility) • Full compliance with SD Memory Card Specifications Version 4.1. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported) • Full compliance with SDIO Card Specification Version 4.0: card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported) • Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO speed) • Data and command output enable signals to control external bidirectional drivers. 3.39 Controller area network (FDCAN) The controller area network (CAN) subsystem consists of one CAN modules and message RAM memory. The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. A 1 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers. 3.40 Universal serial bus (USB FS) The devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 link power management. It has software-configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume support. This interface requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator (HSI48) in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 3.41 USB Type-C™ / USB Power Delivery controller (UCPD) The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications. |
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