A6986HTR datasheet(3/71 Pages) STMICROELECTRONICS

3 / 71 page

Pin settings

2.1

Pin connection

Figure 2. Pin connection (top view)

RST

VCC

SS/INH

SYNCH/ISKIP

FSW

MLF

COMP

DELAY

VBIAS

VIN

PGND

SGND

VOUT

EXPOSED

PAD TO

SGND+PGND

2.2

Pin description

Table 1. Pin description

N°

Description

RST

The RST open collector output is driven low when the output voltage is out of regulation. The

RST is released after an adjustable time DELAY once the output voltage is over the active

delay threshold.

VCC

Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies

the embedded analog circuitry.

SS/INH

An open collector stage can disable the device clamping this pin to GND (INH mode). An

internal current generator (4 µA typ.) charges the external capacitor to implement the soft-

start.

SYNCH/ ISKP

The pin features master / slave synchronization in LNM (see Section 5.8.1 ) and skip current

level selection in LCM (see Section 5.8.2 ). In LNM, leave this pin floating when it is not

used.

FSW

A pull-up resistor (E24 series only) to VCC or pull down to GND selects the switching

frequency. Pin strapping is active only before the soft-start phase to minimize the IC

consumption.

MLF

A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the low consumption

mode/low noise mode and the active RST threshold. Pin strapping is active only before the

soft-start phase to minimize the IC consumption.

COMP

Output of the error amplifier. The designed compensation network is connected at this pin.

DELAY

An external capacitor connected to this pin sets the time DELAY to assert the rising edge of

the RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST

is like a Power Good.

VOUT

Output voltage sensing

SGND

Signal GND

PGND

Power GND

PGND

Power GND

A6986H

Pin settings

DS12861 - Rev 3

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