RX113 datasheet(83/131 Pages) RENESAS

83 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 83 of 131

Sep 07, 2020

RX113 Group

5. Electrical Characteristics

Note:

When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.

Note 1. Oscillators continue oscillating in deep sleep mode.

Note 2. When the frequency of the system clock is 32 MHz.

Note 3. When the frequency of the system clock is 12 MHz.

Note 4. When the frequency of the system clock is 32.768 kHz.

Figure 5.30

Deep Sleep Mode Recovery Timing

Note:

When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.

Table 5.27

Timing of Recovery from Low Power Consumption Modes (4)

Conditions: 1.8 V

≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T

a = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Recovery time from deep

sleep mode*1

High-speed mode*2

tDSLP

—2

3.5

µs

Middle-speed mode*3

tDSLP

—3

µs

Low-speed mode*4

tDSLP

—

400

500

µs

Table 5.28

Timing of Recovery from Low Power Consumption Modes (5)

Operating Mode Transition Time

Conditions: 1.8 V

≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, T

a = –40 to +105°C

Mode before Transition

Mode after Transition

ICLK Frequency

Transition Time

Unit

Min.

Typ.

Max.

High-speed operating mode

Middle-speed operating mode

8 MHz

—

µs

Middle-speed operating mode

High-speed operating mode

8 MHz

—

37.5

—

µs

Low-speed operating mode

Middle-speed operating mode,

high-speed operating mode

32.768 kHz

—

213.62

—

µs

Middle-speed operating mode,

high-speed operating mode

Low-speed operating mode

32.768 kHz

—

183.11

—

µs

Oscillator

ICLK

IRQ

Deep sleep mode

tDSLP

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