HD404818FS datasheet(23/100 Pages) RENESAS

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HD404818 Series

Table 3 Interrupt Conditions

Interrupt Source

Interrupt Control Bit

INT

Timer A

Timer B

Timer C

Serial

111

IF0

• IM0

100

000

IF1

• IM1

000

IFTA

• IMTA

000

IFTB

• IMTB

***

100

IFTC

• IMTC

***

IFS

• IMS

***

Note: *Don’t care.

Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If

an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the

second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed

onto the stack. In the third cycle, the instruction is executed after jumping to the vector address.

In each vector address, program the JMPL instruction to branch to the starting address of the interrupt

program. The IF, which caused the interrupt, must be reset by software in the interrupt program.

Instruction

cycles

Instruction

execution

Stacking;

reset of IE

Interrupt

acceptance

JMPL instruction execution

on the vector address

Instruction

execution at

starting address

of the interrupt

routine

Stacking;

vector address

generated

Figure 7 Interrupt Processing Sequence

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