LTC6226/LTC6227

27

Rev 0

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Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PACKAGE DESCRIPTION

3.00

±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40

±0.10

BOTTOM VIEW—EXPOSED PAD

1.65

±0.10

(2 SIDES)

0.75

±0.05

R = 0.125

TYP

2.38

±0.10

(2 SIDES)

1

5

10

6

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25

±0.05

2.38

±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65

±0.05

(2 SIDES)

2.15

±0.05

0.50

BSC

0.70

±0.05

3.55

±0.05

PACKAGE

OUTLINE

0.25

±0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm

× 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

PIN 1 NOTCH

R = 0.20 OR

0.35

× 45°

CHAMFER