TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

23

POST OFFICE BOX 655303

timing requirements

serial port recommended input signals

MIN

MAX

UNIT

tc(MCLK)

Master clock cycle time

95

ns

tr(MCLK)

Master clock rise time

10

ns

tf(MCLK)

Master clock fall time

10

ns

Master clock duty cycle

42%

58%

RESET pulse duration (see Note 12)

800

ns

tsu(DX)

DX setup time before SCLK

↓

20

ns

th(DX)

DX hold time after SCLK

↓

tc(SCLK)/4

ns

MIN

TYP†

MAX

UNIT

tc(SCLK)

Shift clock (SCLK) cycle time

380

ns

tf(SCLK)

Shift clock (SCLK) fall time

3

8

ns

tr(SCLK)

Shift clock (SCLK) rise time

3

8

ns

Shift clock (SCLK) duty cycle

45

55

%

td(CH-FL)

Delay from SCLK

↑ to FSR/FSX/FSD↓

30

ns

td(CH-FH)

Delay from SCLK

↑ to FSR/FSX/FSD↑

35

90

ns

td(CH-DR)

DR valid after SCLK

↑

90

ns

td(CH-EL)

Delay from SCLK

↑ to EODX/EODR↓ in word mode

90

ns

td(CH-EH)

Delay from SCLK

↑ to EODX/EODR↑ in word mode

90

ns

tf(EODX)

EODX fall time

2

8

ns

tf(EODR)

EODR fall time

2

8

ns

td(CH-EL)

Delay from SCLK

↑ to EODX/EODR↓ in byte mode

90

ns

td(CH-EH)

Delay from SCLK

↑ to EODX/EODR↑ in byte mode

90

ns

td(MH-SL)

Delay from MSTR CLK

↑ to SCLK↓

65

170

ns

td(MH-SH)

Delay from MSTR CLK

↑ to SCLK↑

65

170

ns

† Typical values are at TA = 25°C.

NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their

recommended values.