ST7LITE35 datasheet(134/167 Pages) STMICROELECTRONICS

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ST7LITE3

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OPERATING CONDITIONS (Cont’d)

13.3.1.2 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 3.0 to 3.6V

Notes:

1.RCCR1 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ TA =25°C, VDD=3.3V. See “INTERNAL RC

OSCILLATOR ADJUSTMENT” on page 22.

2.Data based on characterization results, not tested in production

3. Measurement made with RC calibrated at 1MHz.

4. Guaranteed by design.

5. Averaged over a 4ms period. After the LOCKED bit is s et, a period of tSTAB is required to reach ACCPLL accuracy

6.After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11 on page 23.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

Internal RC oscillator fre-

quency

RCCR = FF (reset value), TA=25°C, VDD= 3.3V

1600

kHz

RCCR=RCCR11) ,TA=25°C,VDD= 3.3V

995

1000

1005

ACCRC

Accuracy of Internal RC

oscillator when calibrated

with RCCR=RCCR11)2)

TA=25°C, VDD=3.0 to 3.6V

-1

TA=-40 to +85°C, VDD=3.0 to 3.6V

-3

TA=0 to +85°C, VDD=3.0 to 3.6V

-3

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=3.3V

5002)3)

µA

tsu(RC)

RC oscillator setup time

TA=25°C,VDD=3.3V

101)

µs

fPLL

x4 PLL input clock

12)

MHz

tLOCK

PLL Lock time6)

tSTAB

PLL Stabilization time6)

ACCPLL

x4 PLL Accuracy

fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V

0.15)

fRC = 1MHz@TA=-40 to +85°C, VDD= 3.3V

0.15)

tw(JIT)

PLL jitter period

fRC = 1MHz

84)

kHz

JITPLL

PLL jitter (

∆f

CPU/fCPU)

14)

IDD(PLL)

PLL current consumption TA=25°C

4502)

µA

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