11 Application Curves

Frequency - MHz

-20

0

20

40

60

80

-2

0

2

4

6

8

10

D003

Icc 1.8V

Icc 2.5V

Icc 3.3V

Icc 5V

12 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass

capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel.

The bypass capacitor must be installed as close to the power pin as possible for best results

13 Layout

13.1 Layout Guidelines

When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of

digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3

of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at

the outside connections result in undefined operational states. Specified below are the rules that must be

observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low

bias to prevent them from floating. The logic level that must be applied to any particular unused input depends

convenient.

13.2 Layout Example

Unused Input

Input

Output

Output

Input

Unused Input

Figure 13-1. Layout Example

SN74LVC2G08-Q1

SCES557E – MARCH 2004 – REVISED OCTOBER 2020

www.ti.com

12

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