Functional Description

The 74ACT164 is an edge-triggered 8-bit shift register with

serial data entry and an output from each of the eight

stages Data is entered serially through one of two inputs (A

or B) either of these inputs can be used as an active High

Enable for data entry through the other input An unused

input must be tied High

Each Low-to-High transition on the Clock (CP) input shifts

AND of the two data inputs (A

rising clock edge A Low level on the Master Reset (MR)

input overrides all other inputs and clears the register asyn-

chronously forcing all Q outputs Low

Function Table

Operating

Inputs

Outputs

Mode

MR

Reset (Clear)

L

X

X

L

L – L

Shift

H

L

L

L

HL

H

L

HH

L

L

HH

H

H

output one setup time prior to the Low-to-High clock transition

Logic Diagram

TLF11553 – 3

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

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