MAS3529F datasheet(2/92 Pages) MICRONAS

2 / 92 page

June 30, 2004; 6251-505-1DS

Micronas

Contents

Page

Section

Title

MAS 35x9F

DATA SHEET

Introduction

61.1.

Features

1.2.

Features of the MAS 35x9F Family

1.3.

Application Overview

Functional Description

2.1.

Overview

2.2.

Architecture of the MAS 35x9F

2.3.

DSP Core

2.3.1.

RAM and Registers

2.3.2.

Firmware and Software

2.3.2.1.

Internal Program ROM and Firmware, MPEG-Decoding

2.3.2.2.

Program Download Feature

2.4.

Audio Codec

2.4.1.

A/D Converter and Microphone Amplifier

2.4.2.

Baseband Processing

2.4.2.1.

Bass, Treble, and Loudness

2.4.2.2.

Micronas Bass (MB)

2.4.2.3.

Automatic Volume Control (AVC)

2.4.2.4.

Balance and Volume

2.4.3.

D/A Converters

2.4.4.

Output Amplifiers

2.5.

Clock Management

2.5.1.

DSP Clock

2.5.2.

Clock Output At CLKO

2.6.

Power Supply Concept

2.6.1.

Power Supply Regions

2.6.2.

DC/DC Converters

2.6.3.

Power Supply Configurations

2.7.

Battery Voltage Supervision

2.8.

Interfaces

2.8.1.

I2C Control Interface

2.8.2.

S/PDIF Input Interface

2.8.3.

S/PDIF Output

2.8.4.

Multiline Serial Audio Input (SDI, SDIB)

2.8.5.

Multiline Serial Output (SDO)

2.8.6.

Parallel Input/Output Interface (PIO)

2.9.

MPEG Synchronization Output

2.10.

MP3 Block Input Mode

2.10.1.

Functional Description of the MP3 Block Input Mode

2.10.2.

Setup

2.10.2.1.

Resync Timeout

2.10.2.2.

Detailed Setup

2.11.

Default Operation

2.11.1.

Stand-by Functions

2.11.2.

Power-Up of the DC/DC Converters and Reset

2.11.2.1.

Important Advice for Turn-on and Operating Voltage

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