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MAS3549F bảng dữ liệu(PDF) 33 Page - Micronas

tên linh kiện MAS3549F
Giải thích chi tiết về linh kiện  MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
PDF  92 Pages
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nhà sản xuất  MICRONAS [Micronas]
Trang chủ  http://www.micronas.com
Logo MICRONAS - Micronas

MAS3549F bảng dữ liệu(HTML) 33 Page - Micronas

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DATA SHEET
MAS 35x9F
Micronas
June 30, 2004; 6251-505-1DS
33
Table 3–9: D0 control memory cells
Memory
Address
(hex)
Function
Name
D0:346
Main I/O Control (reset = 8025
hex)
MPEG
IOControlMain is used for selecting/deselecting the appropriate data input
interface and for setting up the serial data output interface. In serial input
mode the coded audio data (Layer 2, Layer 3, AAC) is expected at the serial
input interface SDIB (default). In the 8-bit-parallel input mode the PIO pins
PI[19:12] are used.
bit[15]
MP3 block input selection
0: MP3 block input mode OFF
1: MP3 block input mode ON
bit[14]
Invert serial output clock (SOC)
0 (reset)
do not invert SOC
1invert SOC
bit[13:12]
Reserved, must be set to zero
bit[11]
Serial data output delay
0 (reset)
no additional delay (reset)
1
additional delay of data related to word strobe
bit[10]
Reserved, must be set to zero
bit[9:8]
Input Select Main
00 (reset)
serial input at interface B
01
parallel input at PIO pins PI[19...12]
10
reserved for future use
11
reserved for future use
bit[7:6]
Reserved, must be set to zero
bit[5]
SDO Word Strobe Invert
0
do not invert
1 (reset)
invert outgoing word strobe signal
bit[4]
Bits per Sample at SDO
0 (reset)
32 bits/sample
1
16 bits/sample
bit[3]
Reserved, must be set to zero
bit[2]
Serial data input interface B clock invert (pin SIBC)
0
not inverted (data latched at rising clock edge)
1 (reset)
incoming clock signal is inverted (data latched at
falling clock edge)
bit[1]
0 (reset)
DEMAND MODE (PLL off, MAS 35x9F is clock
master)
1
BROADCAST MODE (PLL on, clock of MAS 35x9F
locks on data stream)
bit[0]
Validate
no forced evaluation of control memory cells
0 (reset)
1
changes in control memory will become effective
Bit[0] is reset after the DSP has recognized the changes. The controller
should set this bit after the other D0 control memory cells have been initialized
with the desired values.
IOControlMain



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