ADAR2004 datasheet(5/37 Pages) AD

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Data Sheet

ADAR2004

Rev. 0 | Page 5 of 37

TIMING SPECIFICATIONS

VPOS1, VPOS2, VPOS4 = 2.5 V, VPOS3 = VREG, and TA = −40°C to +85°C, unless otherwise noted. See Figure 2 to Figure 4 for the timing diagrams.

Table 2. SPI Timing

Parameter

Description

Test Conditions/Comments

Min

Typ

Max

Unit

fSCLK

Maximum clock rate

Write only

MHz

Write and read

MHz

tPWH

Minimum pulse width high

tPWL

Minimum pulse width low

tDS

Setup time, SDIO to SCLK

tDH

Hold time, SDIO to SCLK

tDV

Data valid, SDO to SCLK

tDCS

Setup time, CS to SCLK

SDIO, SDO rise time

Outputs loaded with 10 pF, 10% to 90%

SDIO, SDO fall time

Outputs loaded with 10 pF, 10% to 90%

Timing Diagrams

DON’T CARE

SDIO

SCLK

DON’T CARE

R/W

A14

A13

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

Figure 2. SPI Transaction Structure (MSB First)

DON’T CARE

SDIO

SCLK

WRITE

A14

A13

tDS

tPWL

tPWH

tDCS

tDH

Figure 3. SPI Write Timing Diagram

DON’T CARE

SDIO

SDO

SCLK

READ

A14

A13

tDV

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

Figure 4. SPI 4-Wire Read Timing Diagram

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