DP83TG720SWRHATQ1 datasheet(50/199 Pages) TI

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7.5.2 LED Configuration

The DP83TG720S-Q1 supports up to three configurable Light Emitting Diode (LED) pins: LED_0, LED_1, and

LED_2 (CLKOUT). Several functions can be multiplexed onto the LEDs for different modes of operation. LED

operations are selected using registers 0x0450 and 0x0451.

Note

CLKOUT has 25MHz clock output as default and needs to be configured to LED2 using register

0x0453.

Because the LED output pins are also used as strap pins, external components required for strapping and the

user must consider the LED usage to avoid contention. Specifically, when the LED outputs are used to drive

LEDs directly, the active state of each output driver is dependent on the logic level sampled by the

corresponding input upon power up or hardware reset.

Figure 7-20 shows the two proper ways of connecting LEDs directly to the DP83TG720S-Q1.

Strap Pin

Pull-Up

Strap Pin

Pull-Down

VDDIO

RCL

Figure 7-20. Example Strap Connections

7.5.3 PHY Address Configuration

The DP83TG720S-Q1 can be set to respond to any of 9 possible PHY addresses through bootstrap pins. The

PHY address is latched into the device upon power-up or hardware reset. Each DP83TG720S-Q1 or port

sharing PHY on the serial management bus in the system must have a unique PHY address. The DP83TG720S-

Q1 supports PHY address as described in Table 7-19.

By default, the DP83TG720S-Q1 will latch to a PHY address of 0 ([0000]). This address can be changed by

adding pullup resistors to bootstrap pins found in Table 7-17.

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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