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Register description
IIS2DLPC
50/69
DocID031788 Rev 4
8.6
CTRL3 (22h)
Control register 3 (r/w)
Table 35. Control register 3
Table 36. Control register 3 description
ST2
ST1
PP_OD
LIR
H_LACTIVE
0
SLP_
MODE_SEL
SLP_
MODE_1
ST[2:1]
Self-test enable. Default value: 00
(00: Self-test disabled; Other: see Table 37)
PP_OD
Push-pull/open-drain selection on interrupt pad. Default value: 0
(0: push-pull; 1: open-drain)
LIR
Latched Interrupt. Switches between latched ('1'-logic) and pulsed ('0'-logic) mode for
function source signals and interrupts routed to pins (wakeup, single/double-tap).
Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
H_LACTIVE
Interrupt active high, low. Default value: 0
(0: active high; 1: active low)
SLP_
MODE_SEL
Single data conversion on demand mode selection:
0: enabled with external trigger on INT2;
1: enabled by I2C/SPI writing SLP_MODE_1 to 1.
SLP_
MODE_1
Single data conversion on demand mode enable. When SLP_MODE_SEL = '1' and
this bit is set to '1' logic, single data conversion on demand mode starts. When XL
data are available in the registers, this bit is set to '0' automatically and the device is
ready for another triggered session.
Table 37. Self-test mode selection
ST2
ST1
Self-test mode
0
0
Normal mode
0
1
Positive sign self-test
1
0
Negative sign self-test
11-



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