USB3343CPTR datasheet(9/92 Pages) MICROCHIP

9 / 92 page

 2009-2018 Microchip Technology Inc.

DS00002646A-page 9

USB334x

RESETB

Input,

CMOS,

Low

When low, the part is suspended and the 3.3V and

1.8V regulators are disabled. When high, the

USB334x will operate as a normal ULPI device, as

described in Section 5.6.2. The state of this pin may

be changed asynchronously to the clock signals.

When asserted for a minimum of 1 microsecond and

then de-asserted, the ULPI registers are reset to

their default state and all internal state machines are

reset.

VDD18

Power

N/A

1.8V Regulator Output. A 1.0uF (<1 ohm ESR)

bypass capacitor to ground is required for regulator

stability. The bypass capacitor should be placed as

close as possible to the USB334x.

STP

Input,

CMOS

High

The Link asserts STP for one clock cycle to stop the

data stream currently on the bus. If the Link is

sending data to the PHY, STP indicates the last byte

of data was on the bus in the previous cycle.

DIR

Output,

CMOS

N/A

Controls the direction of the data bus. When the PHY

has data to transfer to the Link, it drives DIR high to

take ownership of the bus. When the PHY has no

data to transfer it drives DIR low and monitors the

bus for commands from the Link.

FLAG

GND

Ground

N/A

Ground.

TABLE 2-1:

USB3341, USB3346, AND USB3347 PIN DESCRIPTIONS (CONTINUED)

Name

Direction/

Type

Active

Level

Description

USB3343CPTR bảng dữ liệu(PDF) 9 Page - Microchip Technology

USB3343CPTR bảng dữ liệu(HTML) 9 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

bảng dữ liệu tải về

Link URL