MCP1633 datasheet(15/31 Pages) MICROCHIP

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DS20006289A-page 15

MCP1633

4.0

DETAILED DESCRIPTION

4.1

Device Overview

The MCP1633 device integrates all the functions

needed for designing a compact LED driver based on

low side topologies. The device uses peak current

mode control technique to achieve constant output

current and fast transient response. The output current

level is set by the analog adjust, SS/REF by using a

simple resistor or external voltage to achieve analog

dimming. PWM dimming is also supported by

specialized internal block using an external PWM

signal with 0 to 100%. The integrated low offset, current

sense amplifier provides the flexibility due to differential

type and external gain set. The output of the current

sense amplifier can be used to close the loop and

measure the output current. The application's safety is

achieved by internal protections UVLO, OVLO and

thermal shutdown turning off the converter and

disconnecting the load and reporting the status via

FAULT pin which is open drain indicator.

4.2

PWM Circuitry

MCP1633 implements a typical Peak Current Mode

control loop. The VEXT output of the MCP1633 device

is determined by the output level of the internal high-

speed comparator and the level of the internal CLK

signal. When the CLK signal level is high, the PWM

output (VEXT) is forced low, limiting the maximum duty

cycle to approximately 90% (typical). When the CLK

signal is low, the PWM output is determined by the

output level of the internal high-speed comparator.

During UVLO and OVLO, the VEXT pin is held in low

state. During overtemperature operation, the VEXT pin

is high-impedance (10 kΩ to ground, typical).

4.3

Normal Cycle-by-Cycle Control

The beginning of a PWM cycle is defined by the internal

CLK signal (a transition from high to low). Refer to

Figure 4-1 for the detailed timing operation of the

MCP1633 PWM controller. For normal operation, the

state of the high-speed comparator output (R) is low

and the Q output of the latch is low. On the high-to-low

transition of the CLK signal, the SR inputs to the high-

speed latch are both low and the Q output will remain

unchanged (low). The output of the OR gate (VDRIVE)

will transition from high to low, turning on the P-Chan-

nel drive transistor in the output stage of the PWM. This

will change the PWM output (VEXT) from low to high,

turning on the power train MOSFET and ramping

current in the power train magnetic device. The sensed

current in the magnetic device is fed into the CS input,

shown as a ramp, and increases linearly until it reaches

the same level as the divided down output of the error

amplifier at the noninverting input of the high-speed

comparator. The comparator output (R) changes state

(low to high) and resets the PWM latch. The Q output

transition from low to high turns off the VEXT drive to the

external MOSFET driver, thus terminating the current

conduction cycle. The CLK signal will transition from

low to high while the VEXT pin remains unchanged. If

the CS input pin never reaches the same level as the

error amplifier output, the low-to-high transition on the

CLK signal terminates the current switching cycle. This

would be considered as the maximum duty cycle. In

either case, while the CLK signal is high, the VEXT drive

pin is low, turning off the external power train switch.

The next switching cycle will start on another transition

of the CLK signal from high to low.

FIGURE 4-1:

PWM Timing Diagram.

CLK

EA Out

ISENSE

Comp

Out

VDRIVE

VEXT

Ramp

Signal

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