ASP00886IRGCT datasheet(3/139 Pages) TI

3 / 139 page

4 Functional Block Diagrams

Figure 4-1 shows the functional block diagram for the MSP430F5529, MSP430F5527, MSP430F5525, and

MSP430F5521 devices in the PN package.

Unified

Clock

System

128KB

96KB

64KB

32KB

Flash

8KB+2KB

6KB+2KB

4KB+2KB

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1, P2

2×8 I/Os

Interrupt,

Wakeup

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG,

SBW

Interface

DMA

3 channels

XT2IN

XT2OUT

Power

Management

LDO

SVM, SVS

Brownout

SYS

Watchdog

Port Map

Control

(P4)

I/O Ports

P3, P4

2×8 I/Os

1×16 I/Os

I/O Ports

P5, P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7, P8

1×8 I/Os

1×3 I/Os

1×11 I/Os

Full-speed

USB

USB-PHY

USB-LDO

USB-PLL

MPY32

TA0

Timer_A

5 CC

Registers

TA1

Timer_A

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_A

CRC16

USCI0,1

USCI_Ax:

UART,

IrDA, SPI

USCI_Bx:

SPI, I C

ADC12_A

12 Bit

200 ksps

16 Channels

(14 ext, 2 int)

Autoscan

DVCC DVSS

AVCC AVSS

P1.x

P2.x

P3.x

P4.x

P5.x

P6.x

DP,DM,PUR

RST/NMI

TA2

Timer_A

3 CC

Registers

REF

VCORE

MAB

MDB

P7.x

P8.x

COMP_B

12 channels

Figure 4-1. Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,

MSP430F5521IPN

Figure 4-2 shows the functional block diagram for the MSP430F5528, MSP430F5526, MSP430F5524, and

MSP430F5522 devices in the RGC, ZXH, and ZQE packages and for the MSP430F5528 device in the YFF

package.

Unified

Clock

System

128KB

96KB

64KB

32KB

Flash

8KB+2KB

6KB+2KB

4KB+2KB

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1, P2

2×8 I/Os

Interrupt,

Wakeup

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG,

SBW

Interface

DMA

3 channels

XT2IN

XT2OUT

Power

Management

LDO

SVM, SVS

Brownout

SYS

Watchdog

Port Map

Control

(P4)

I/O Ports

P3, P4

1×5 I/Os

1×8 I/Os

1×13 I/Os

I/O Ports

P5, P6

1×6 I/Os

1×8 I/Os

1×14 I/Os

Full-speed

USB

USB-PHY

USB-LDO

USB-PLL

MPY32

TA0

Timer_A

5 CC

Registers

TA1

Timer_A

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_A

CRC16

USCI0,1

USCI_Ax:

UART,

IrDA, SPI

USCI_Bx:

SPI, I C

ADC12_A

12 Bit

200 ksps

12 Channels

(10 ext, 2 int)

Autoscan

DVCC DVSS

AVCC AVSS

P1.x

P2.x

P3.x

P4.x

P5.x

P6.x

DP,DM,PUR

RST/NMI

TA2

Timer_A

3 CC

Registers

REF

VCORE

MAB

MDB

COMP_B

8 channels

Figure 4-2. Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,

MSP430F5522IRGC,

MSP430F5528IZXH, MSP430F5526IZXH, MSP430F5524IZXH, MSP430F5522IZXH,

MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE,

MSP430F5528IYFF

www.ti.com

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526, MSP430F5525, MSP430F5524,

MSP430F5522, MSP430F5521, MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514,

MSP430F5513

SLAS590P – MARCH 2009 – REVISED SEPTEMBER 2020

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525

MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514

MSP430F5513

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